AES in CDL Part 2 - Key Scheduling in Verilog

This post is the second in my series on the AES crypto algorithm and my implementation of it in CDL. In this post, I cover my Verilog implementation of the AES-256 key schedule.

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AES in CDL Part 1 - Key Schedule in Python

I began implementing the Advanced Encryption Standard (AES) encryption algorithm in Verilog with the intention of creating a configurable digital logic (CDL) encryption engine. This post, the first in a series, covers the key expansion (key scheduling) portion of the implementation.

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DES in CDL: Part 5- Integrating with Software on the Zynq7000

In this post, I continue my CDL implementation of the DES encryption algorithm by integrating the IP as an AXI peripheral accessible to software running on the Zynq processing system.

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DES in CDL: Part 4 - A 3DES (Triple DES) Wrapper

This post is continuation of my Verilog implementation of the DES encryption algorithm. In this post, I wrapped my DES IP block in a 3DES implementation

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DES in CDL: Part 3 - Decryption, Data Pipe-lining, Useful Interface

This post is continuation of my Verilog implementation of the DES encryption algorithm. In this post, I added support for the decryption operation, restructured the code to use data pipe-lining and provided a usable interface to the module: enable/disable, mode selection (encryption/decryption) and a validity bit to indicate a complete operation.

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