In this post I created a simple CDL module to test a memory-like interface for moving data between the programmable logic and processing system of the Zynq7000

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In this post I cover creating a simple memory-like AXI-4 interface between the Zynq7000 programmable logic and DDR. I intend to expand on this interface to facilitate a data path for my CDL encryption algorithm implementations.

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This post is the fourth in my series on the AES crypto algorithm and my implementation of it in CDL. In this post, I described my implementation of the encryption portion of the algorithm in Verilog.

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This post is the third in my series on the AES crypto algorithm and my implementation of it in CDL. In this post, I described my implementation of the encryption portion of the algorithm in Python and some of the mathematical basis for the steps.

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This post is the second in my series on the AES crypto algorithm and my implementation of it in CDL. In this post, I cover my Verilog implementation of the AES-256 key schedule.

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